balaji comment FHDL CODE FOR A 2 PROCESSOR ARRAY TO COMPUTE JOIN comment DEVELOPED by K.R.BALAJI comment DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING comment UNIVERSITY OF SOUTH FLORIDA, TAMPA, FL 33620. comment MACRO TO PRINT RESULTS ONTO TO OUTPUT FILES. prnt: 'macro go; monitor 0,pr0r1,pr1r1,pr0rega,pr0regb,pr0regt writexd 7,pr0la,pr0lb,pr0lt,pr1la,pr1lb,pr1lt writexd 8,pr0r0,pr0r1,pr0r2,pr1r0,pr1r1,pr1r2 writexd 9,pr0rega,pr0regb,pr1rega,pr1regb,pr0regt,pr1regt,pr0rega0, pr0regb0,pr1rega,pr1regb0 'endmacro main: driver variable inc,incr,ince,coun readd 1,pr0lin,pr0lin1,clk,pr0din,pr0din1,pr1lin,pr1lin1, pr1din,pr1din1,pr0dlst,pr1dlst comment CODE TO EXECUTE VARIOUS PHASES OF SYSTOLIC ALGORITHM FOR JOIN while inc!=2 readd 2,pr0rega prnt readd 3,pr1regb prnt inc+1->inc endwhile 0->ince 0->ince while ince!=2 readd 4,pr1regb prnt ince+1->ince endwhile 5->coun 0->incr while incr!=2 0->inc readd coun,pr0rega while eof(coun)!=1 prnt readd coun,pr0rega endwhile 0->ince while ince!=1 readd 4,pr1regb prnt ince+1->ince endwhile coun+1->coun incr+1->incr endwhile 0->inc readd 4,eod,pr1regb while inc!=2 go writexd 9,pr0rega,pr0regb,pr1rega,pr1regb,pr0regt,pr1regt, pr0rega0,pr0regb0,pr1rega,pr1regb0 writexd 7, pr0la,pr0lb,pr0sel,pr0lt inc+1->inc endwhile enddriver comment LOGIC FOR PROCESSOR PE0 comment SIGNALS WITH PREFIX "PR0" BELONG TO FIRST PROCESSING ELEMENT comment 7-bit counter circuit inputs pr0lin,pr0lin1,clk,pr0din,pr0din1,pr0dlst,pr1dlst,eod inputs pr0rega,pr1regb outputs pr0lout,pr0lout1,pr0lout2 comment 24bit registers for storing and wire pr0lin,width=24 wire pr0lout,width=24 wire pr0lout1,width=24 wire pr0lout2,width=24 wire pr0lin1,width=24 regnk0: register (pr0lin,clk,clk),(pr0lout), clock=yes regk0: register (pr0lin1,clk,clk),(pr0lout1),clock=yes mux (pr0lout,pr0lout1,pr0cnt1),pr0lout2 comment 7 bit counter wire pr0din,width=2 wire pr0cm,width=3 wire pr0cnt7o,width=2 nand (pr0c0,pr0c1),pr0o1 not pr0o1,pr0cr0bar not pr0o1,pr0cnt7ld distribute pr0cnt7o,(pr0c0,pr0c1) counter (pr0din,pr0cnt7ld,pr0clk0),(pr0cnt7o,pr0staone), control=(load),dataout=yes,status=all_ones,clock=yes not pr0staone,pr0clk0 jkff (pr0cr0bar,pr0o1,pr0cr0bar),pr0cr1 comment 24-bit counter outputs pr0cmn,pr0cmo,pr0cmp outputs pr0la,pr0lb,pr0sel,pr0lt wire pr0din1,width=24 wire pr0cnt24o,width=24 not pr0cmo,pr0cmobar dff (pr0cr0bar,pr0cmobar),pr0crbdff nand (pr0cmobar,pr0crbdff),pr0cnt24ld counter (pr0din1,pr0cnt24ld,pr0clk1),(pr0cnt24o,stone), control=(load),dataout=yes,status=all_ones,clock=yes not stone,pr0clk1 comparator (pr0lout2,pr0cnt24o),(pr0cm) distribute pr0cm,(pr0cmn,pr0cmo,pr0cmp) comment code for 1-bit counter outputs pr0cnt1 not clk,clkbar tff1 (pr0cmo,clk,clkbar),(pr0tffo) dff (pr0tffo,pr0cmo),pr0cnt1 comment Code for generating control signals for last k cycles wire pr0dlst,width=2 wire pr0dlso,width=2 nand (pr0ls1,pr0ls2),pr0ldlst not pr0ldlst,pr0ldlstb distribute pr0dlso,(pr0ls1,pr0ls2) counter (pr0dlst,pr0ldlst,eod),(pr0dlso), control=(load),dataout=yes,clock=yes mux (pr0cr1,pr0ldlst,eod),pr0cr2 mux (pr0cnt1,pr0ldlstb,eod),pr0cnt2 comment Generation of pr0la,pr0lb,pr0sel and pr0lt not pr0c1,pr0la1 nor (pr0c1,pr0cmobar),pr0sel1 wire pr0bus0,width=4 wire pr0bus1,width=4 collect (pr0la1,pr0c1,pr0sel1,pr0c1),pr0bus0 wire pr0bus2,width=4 wire pr0bus3,width=4 wire pr0bussel,width=4 zero la2,sel2,lt2 one lb2 one lb3 one la3 one prsel3 collect (la2,lb2,sel2,lt2),pr0bus2 or (pr0la,pr0cnt1),pr0sys dff (prsel3,pr0sys),pr0sel3 collect (la3,lb3,pr0sel3,lt2),pr0bus3 mux (pr0bus2,pr0bus3,pr0cnt2),pr0bus1 mux (pr0bus0,pr0bus1,pr0cr2),pr0bussel distribute pr0bussel,(pr0la,pr0lb,pr0sel,pr0lt) comment PROCESSING LOGIC FOR "PE 0" outputs pr0r0,pr0r1,pr0r2 wire pr0rega,width=32 wire pr0rega0,width=32 wire pr0regb,width=32 wire pr1rega,width=32 wire pr1regb,width=32 wire pr1regb0,width=32 wire pr0regb0,width=32 wire pr0regt,width=32 wire pr0r,width=3 register (pr0rega,pr0la,clk),(pr0rega0), clock=yes regt0: register (pr1regb0,pr0lt,clk),(pr0regt), clock=yes muxa0: mux (pr1regb0,pr0regt,pr0sel),pr0regb register (pr0regb,pr0lb,clk),(pr0regb0) comparator (pr0rega0,pr0regb0),(pr0r) distribute pr0r,(pr0r0,pr0r1,pr0r2) comment LOGIC FOR PROCESSOR PE 1 comment SIGNALS WITH PREFIX "PR1" BELONG TO 2nd PROCESSING ELEMENT. comment 7-bit counter inputs pr1lin,pr1lin1,pr1din,pr1din1 outputs pr1lout,pr1lout1,pr1lout2 comment 24bit registers for storing and wire pr1lin,width=24 wire pr1lout,width=24 wire pr1lout1,width=24 wire pr1lout2,width=24 wire pr1lin1,width=24 regnk1: register (pr1lin,clk,clk),(pr1lout), clock=yes regk1: register (pr1lin1,clk,clk),(pr1lout1),clock=yes mux (pr1lout,pr1lout1,pr1cnt1),pr1lout2 comment 7 bit counter wire pr1din,width=2 wire pr1cm,width=3 wire pr1cnt7o,width=2 nand (pr1c0,pr1c1),pr1o1 not pr1o1,pr1cr0bar not pr1o1,pr1cnt7ld distribute pr1cnt7o,(pr1c0,pr1c1) counter (pr1din,pr1cnt7ld,pr1clk0),(pr1cnt7o,pr1staone), control=(load),dataout=yes,status=all_ones,clock=yes not pr1staone,pr1clk0 jkff (pr1cr0bar,pr1o1,pr1cr0bar),pr1cr1 comment 24-bit counter outputs pr1cmn,pr1cmo,pr1cmp outputs pr1la,pr1lb,pr1sel,pr1lt wire pr1din1,width=24 wire pr1cnt24o,width=24 not pr1cmo,pr1cmobar dff (pr1cr0bar,pr1cmobar),pr1crbdff nand (pr1cmobar,pr1crbdff),pr1cnt24ld counter (pr1din1,pr1cnt24ld,pr1clk1),(pr1cnt24o,stone), control=(load),dataout=yes,status=all_ones,clock=yes not stone,pr1clk1 comparator (pr1lout2,pr1cnt24o),(pr1cm) distribute pr1cm,(pr1cmn,pr1cmo,pr1cmp) comment code for 1-bit counter outputs pr1cnt1 not clk,clkbar tff1 (pr1cmo,clk,clkbar),(pr1tffo) dff (pr1tffo,pr1cmo),pr1cnt1 comment Code for generating control signals for last 'k' cycles wire pr1dlst,width=2 wire pr1dlso,width=2 nand (pr1ls1,pr1ls2),pr1ldlst not pr1ldlst,pr1ldlstb distribute pr1dlso,(pr1ls1,pr1ls2) counter (pr1dlst,pr1ldlst,eod),(pr1dlso), control=(load),dataout=yes,clock=yes mux (pr1cr1,pr1ldlst,eod),pr1cr2 mux (pr1cnt1,pr1ldlstb,eod),pr1cnt2 comment Generation of pr1la,pr1lb,pr1sel and pr1lt not pr1c1,pr1la1 nor (pr1c1,pr1cmobar),pr1sel1 wire pr1bus0,width=4 wire pr1bus1,width=4 collect (pr1la1,pr1c1,pr1sel1,pr1c1),pr1bus0 wire pr1bus2,width=4 wire pr1bus3,width=4 wire pr1bussel,width=4 zero la2,sel2,lt2 one lb2 one lb3 one la3 collect (la2,lb2,sel2,lt2),pr1bus2 or (pr1cmo,pr1cnt1),pr1sys comment or (pr1cnt1,pr1la),pr1sys dff (pr0sel,pr1sys),pr1sel3 collect (la3,lb3,pr1sel3,lt2),pr1bus3 mux (pr1bus2,pr1bus3,pr1cnt2),pr1bus1 mux (pr1bus0,pr1bus1,pr1cr2),pr1bussel distribute pr1bussel,(pr1la,pr1lb,pr1sel,pr1lt) comment PROCESSING LOGIC FOR "PE 1" outputs pr1r0,pr1r1,pr1r2 wire pr1regb,width=32 wire pr1regb0,width=32 wire pr1regt,width=32 wire pr1regbin,width=32 wire pr1r,width=3 rega1: register (pr0rega0,pr1la,clk),(pr1rega), clock=yes regt1: register (pr1regb,pr1lt,clk),(pr1regt), clock=yes muxa1: mux (pr1regb,pr1regt,pr1sel),pr1regbin register (pr1regbin,pr1lb,clk),pr1regb0 comparator (pr1rega,pr1regb0),(pr1r) distribute pr1r,(pr1r0,pr1r1,pr1r2) endcircuit