The FHDL PLA specification language allows one to specify the number of inputs, the number of outputs, and the contents of the AND and OR plane portion of each wordline. See Chapter IV for a more sophisticated PLA specification language. The contents of the AND plane must be specified in trinary where 0 and 1 represent a bit test against the specified value and x represents don't care. The trinary string is normally enclosed in quotes. The contents of the OR plane must be specified in hexadecimal.
In FHDL, a PLA is a circuit containing only "plaword" statements and input/output declarations. The following is an example.
| pla1: | circuit | |
| inputs | a1 | |
| outputs | plaout | |
| wire | a1,width=8 | |
| wire | plaout,width=16 | |
| plaword | "0111xxxx",7ffe | |
| plaword | "x010x01x",8000 | |
| plaword | "011x0xxx",0001 | |
| plaword | "0111101x",07ff | |
| endcircuit |
As this example shows, each "plaword" instruction supplies the AND and OR plane values for one wordline of the PLA. OR plane values must be specified in hexadecimal, without the "0x" prefix. There must be at least one input and at least one output, and each input and output should have a declared width. The maximum width for any input or output is 32. PLAs with more than 32 inputs and outputs may be constructed using multiple inputs and outputs. When a PLA has multiple inputs and outputs, each "plaword" instruction must specify the value of each input and each output as illustrated below.
| abc: | circuit | |
| inputs | a1,a2 | |
| outputs | o1,o2,o3 | |
| wire | a1,width=2 | |
| wire | a2,width=2 | |
| wire | o1,width=4 | |
| wire | o2,width=4 | |
| wire | o3,width=4 | |
| plaword | "xx","01",a,b,c | |
| plaword | "0x","x0",d,e,f | |
| plaword | "1x","x1",0,1,2 | |
| plaword | "11","xx",3,4,5 | |
| endcircuit |
As both examples illustrate, it is not necessary to specify a value for each set of input conditions. When the FHDL compiler generates simulation code for the pla, the input condition is checked against the conditions specified for each wordline. If no wordline is selected by the condition, a run-time error message is issued. This provides a convenient method for determining whether invalid PLA conditions are being issued.