| register | (datain,load,controlsignals,clock), | |
| (dataout,statussignals), | ||
| options |
Datain and dataout may be a set of n width-1 signals or one width-n bus. Options are of the form option_name=option or option_name=(opt1,opt2,...). The options determine the content of the controlsignals and statussignals fields. The available options are as follows.
| control= | clear (include an asynchronous clear) right (include a shift-right signal) left (include a shift-left signal) set (include an asychronous set) |
These signals appear in the controlsignals field in the order specified. If the control option is not used, there are no signals in the controlsignals field.
| status= | all_zero (include a zero status output) all_ones (include a set status output) |
These signals appear in the statussignals field in the order specified. If status is not specified, there are no signals in the statussignals field.
| clock= | yes (create a clocked register) no (create an async-load register) |
Default is "yes." If "yes" is specified, the clock is always the last input in the input list.
| serial= | right (Include a right serial input) left (Include a left serial input) |
This option adds serial inputs to the controlsignals field. These will appear in the order specified, either at the begining of the controlsignals field or at the end, depending on whether the status or control input is specified first. The right serial input is used for left shifts and the left serial input is used for right shifts.