Recall that the PLA preprocessor prepares data for the FHDL compiler. Since the FHDL compiler cannot handle buses whose width is greater than 32, the inputs and the outputs of the PLA will be grouped into blocks of 32 bits starting from the left. Of course, the last (or only) block may have fewer than 32 bits. Depending on how the inputs and outputs of the PLA are used by the rest of the circuit, it may be convienient to group them differently. The "input" and "output" statements can be used to do this. The operands of the "input" and "output" statements determine how the inputs and outputs of the PLA are grouped. One group of inputs or outputs will be created for each operand. Each operand must be an expression that gives the size of the group. The value of the expression must range from 1 to 32. An example of an input and an output statement is given below.
output awid,bwid,cwid
input condawid,condbwid
The most convenient grouping of inputs and outputs is by field. Note that this grouping is logical rather than physical.