Wire Declarations.

Nets (or signals, as they are often called in this documentation) are self-declaring. You declare a signal by using it as the input or output of a gate. The inputs and outputs statements assign special properties to signals. The wire statement can be used to further alter the characteristics of a net. The default declaration of a net is as a single-bit active-high signal.

A signal may be declared to be active low by using the following statement.

  wire A,type=active_low

The signal A should appear as a connection in some gate of the circuit. Similarly, a signal can be declared as unconnected by using the following statement.

  wire B,type=no_connect

Signals can be declared as permanently one or permanently zero by using one of the following statements.

  zero
one
A,E,F
B,C

A signal can be declared to be a bus, which will cause it to be treated as a collection of independent signals. This option makes coding easier and more readable and makes simulations run faster. To declare a signal as a bus, use the following statement.

  wire A,width=10

The width may be anything from 1 to 32. When a bus is fed into an ordinary gate, the gate will be replicated to match the width of the signal. Different gates treat buses differently, so check the appendix first.

The collect, distribute, and expand statements are used to connect signals and other buses to a bus. The collect statement is used to feed a collection of signals into a bus. An example of a collect statement is given below.

  collect (a,b,c),d

The signals a, b, and c are collected together into the bus d. The three signals may have any width, but the sum of the widths of the inputs cannot be larger than the width of the output. The position parameter can be used to place a, b, and c at specific points within d, as illustrated by the following statement.

  collect (a,b,c),d,position=(1,3,5)

Assuming that the widths of a, b, and c are all 1, this statement inserts a, b, and c into the odd numbered positions of d. Note that the collect statement creates the bus d, so you cannot use several collect statements to build a bus. You have to do it all in one statement. The position parameter treats the leftmost bit of the bus as position zero. No overlap check is done for position parameters, so you must be careful.

The distribute statement is the reverse of the collect statement. It is used to distribute the signals in a bus to several output signals. The following statement distributes the signals in a bus a to two outputs x and y.

  distribute a,(x,y)

The leftmost bits of a are fed to x, and the next bits are fed to y. The width of a must be greater than or equal to the sum of the widths of x and y. The position parameter can be used on the distribute statement in order to specify the location within the input where the bits of an output must start. For example, the following statement extracts the high and low order bits from a 16-bit bus.

  distribute abus,(highbit,lobit),position=(0,15)

The expand statement fans a width-1 signal out into every position of a bus. Assume that the width of the signal a is 1 and the width of signal b is 5. Then the following two statements are equivalent.

  expand a,b
  collect (a,a,a,a,a),b