The FHDL PLA compiler is a preprocessor that provides a simple but powerful language for specifying the contents of a PLA. The format of the PLA preprocessor statements is modeled after that of FHDL statements. Each statement has a label field, an opcode, and an operand field. The label field begins at the first character of the statement and ends with a colon (:). The label field is optional for some types of statements, and manditory for others. The opcode, which is manditory for all statements, follows the label field, and must be separated from the label field by one or more spaces or tabs. If no label field is present, the opcode must be preceded by one or more spaces or tabs to signify that the label field is omitted. The operand field follows the opcode and must be separated from the opcode by one or more spaces or tabs. The operand field consists of one or more operands separated by commas. The format of an operand depends on the type of statement. The operand field, and the statement, end with a newline (return key) or a semicolon(;). The operand field of a statement can be continued to the next line by ending a line with a comma. Spaces and tabs are not allowed in the operand field, except preceeding or following a comma.
Labels may contain upper and lower case letters, numbers, underlines and periods. Labels may not duplicate a PLA preprocessor keyword, nor may duplicate labels be defined, regardless of type. Case is significant for labels, so Lab1, LAb1, and lAb1 are three different labels. On the other hand, case is not significant in keywords, so pla, Pla and PLA are all the same keyword.
Once a PLA description has been completed, it must be run through the PLA preprocessor before being compiled by the FHDL compiler. Although FHDL provides a method for describing the contents of a PLA, the method is not flexible enough for specifying and debugging complex PLAs. Nevertheless, the final section of this report contains a description of the FHDL native method for specifying PLA contents. The PLA preprocessor converts the preprocessor language into FHDL native mode instructions.