| adder | (leftin,rightin),(output) |
Either leftin or right in may be n width-1 signals or a width-n bus. The output may also be n width-1 signals or an width-n bus. The default is to have no carry in and no carry out. The presence of a carry-in is specified by the attribute "carry=in" while the presence of a carry out is specified by the attribute "carry=out." The presence of both is specified by the attribute "carry=(in,out)." If carry in is present, it must follow "rightin" in the input list and must have a width of one. Similarly carry out follows "output" in the output list and must have a width of one. The following is an example with both.
| adder | (leftin,rightin,ci),(output,co),carry=(in,out) |