rsff
dff
dff1
dff2
dff3
dff4
jkff
jkff1
jkff2
jkff3
jkff4
tff
tff1
tff2
tff3
tff4
All flip flops may have one or two outputs. If one output is specified, it is the normal uncomplemented output. If two outputs are specified, the first is the uncomplemented output and the second is the complemented output. The two outputs must have the same width.
The rs flip flop (rsff) has two inputs, set and reset.
The d flip flop (dff) has two inputs, d and clock.
The jk flip flop (jkff) has three inputs, j, k, and clock.
The t flip flop has two inputs toggle and clock.
For these flip flops, the inputs are all active high must be specified in the order given.
Flip-flops of the form dff1, jkff1, and tff1 are CMOS variations on the basic flip-flops. In addition to the inputs already mentioned, each of these must also have an inverted-clock input. Flip-flops ending in 1 have no other inputs in addition to the inverted clock. Those ending in 2 have an active-high asynchronous set, those ending in 3 have an active-low asynchronous reset, and those ending in 4 have both. The additional inputs follow the clock in the following order as appropriate <inverted-clock>,<set>,<reset>.
If the outputs of a flip flop are buses, the gates replicate themselves for each bit in the bus. The width of an input must be 1 or identical to the width of the outputs. If the width of an input is 1, the input is fanned out to all of the replicated gates. Otherwise, the individual bits in the input are routed to the individual flip flops. This replication of gates is logical not physical, so replicated gates usually simulate much faster than a collection of individually specified gates.