| counter | (datain,controlsignals), | |
| (dataout,statussignals), | ||
| options |
The datain and dataout, if present, must be a collection of n width-1 signals, or one width-n bus. The options are the same format as those for registers. The available options are as follows.
| control= | set clear count_up count_down load |
Each option causes one control signal to be included in the controlsignals field in the order specified. If "load" is not included, then "datain" is implicitly omitted. If both count_up and count_down are omitted, the counter will count up with each clock pulse (if the clock is present) or with each input vector (if there is no clock).
| status= | all_zero all_ones |
This is the same as for registers.
| clock= | yes no |
This is the same as for registers.
| dataout= | yes no |
If dataout=no is specified, the dataout field will be omitted. Default is dataout=yes.
| width= | <<number>> |
If both datain and dataout are missing, you must use this parameter to indicate how many bits are in the counter.
| type= | binary decade |
The normal (and default) type of counter is a binary counter. A decade counter counts from zero to nine and back to zero, and must have a width of 4.