All of these gates may be used with buses as long as the widths of all inputs and outputs are identical. The gates replicate themselves for each element of the bus. Replicated gates typically simulate much faster than individually specified gates. All gates except not and buff may have an arbitrary number of inputs, but must have at least two inputs. The not and buff gates must have one input. All of these gates must have one output. Since all of these gates represent symmetric functions, the order of the inputs is not significant. The buff gate is a non-inverting buffer.